Verilog to Routing XML file generation from Verilog (f4pga-v2x)¶
v2x is a tool for converting specialized annotated Verilog models into XML needed for Verilog to Routing flow.
Documentation can be found at https://f4pga-v2x.readthedocs.io/en/latest/.
v2x can be installed from a local git repository using pip.
pip install .
Alternatively, it can be installed from GitHub directly.
pip install git+https://github.com/chipsalliance/f4pga-v2x.git#egg=f4pga-v2x
After installing v2x, you can run
v2x to use it.
usage: __main__.py [-h] [--top TOP] [--outfile OUTFILE] [--includes INCLUDES]
input.v [input.v ...]
Verilog to XML
input.v One or more Verilog input files, that will be passed
to Yosys internally. They should be enough to generate
a flattened representation of the model, so that paths
through the model can be determined.
-h, --help show this help message and exit
--top TOP Top level module, will usually be automatically
determined from the file name im.v
--outfile OUTFILE, -o OUTFILE
Output filename, default 'output.xml'
--includes INCLUDES Comma separate list of include directories.
Output file type, possible values are: pb_type and
model. Default value is pb_type
For example, to generate a pb_type xml file from adder.v, run
v2x -o adder.pb_type.xml adder.v
Or, to generate a model xml file, run
v2x --mode model -o adder.model.xml adder.v
v2x expects the module name to be the same as the file name. If it is different, make sure to specifiy it with the
v2x --top BLOCK -o adder.pb_type.xml adder.v
The test cases are stored in tests/, and pytest can be used to run them.
rm -rf build # run this step so that pytest uses the latest files for the tests
If you are making changes to any python code, make sure that they follow the PEP8 style guide by running flake8.
We use sphinx for our documentation and the files are stored in docs/. To host it locally (if you are planning to update it), you can use the Makefile inside.
make env to prepare a Conda environment that contains the necessary packages to build and host the documentation site. After that, simply run
make livehtml which starts a local server running at port 8000 with the documentation site.
VPR device models generation from Verilog with V2X - Karol Gugala - ORConf 2019