Classical D-Flip-Flop test

An example of the classical D-Flip-Flop shown in Figure 60 - DFF.

Figure 60 from Verilog to Routing Documentation

Fig. 60 - DFF



dff.sim.v
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`ifndef DFF
`define DFF

(* whitebox *)
module DFF (D, CLK, Q);

  input wire CLK;

  (* SETUP="CLK 10e-12" *)
  (* HOLD="CLK 10e-12" *)
  input wire D;

  (* CLK_TO_Q="CLK 10e-12" *)
  output reg Q;

  always @ ( posedge CLK ) begin
    Q <= D;
  end

`ifndef YOSYS
  specify
    specparam
      tplh$CLK$QP = 1.0,
      tphl$CLK$QP = 1.0,
      tplh$CLK$QN = 1.0,
      tphl$CLK$QN = 1.0,
      tsetup$D$CLK = 1.0,
      thold$D$CLK = 1.0,
      tminpwl$CLK = 1.0,
      tminpwh$CLK = 1.0;

    // PATH DELAYS
    if (flag)
      // Polarity of QP is positive referenced to D
      (posedge CLK *> (QP +: D)) = (tplh$CLK$QP, tphl$CLK$QP);
    if (flag)
      // Polarity of QN is negative referenced to D
      (posedge CLK *> (QN -: D)) = (tplh$CLK$QN, tphl$CLK$QN);

    // SETUP AND HOLD CHECKS
    $setuphold(posedge CLK &&& (flag == 1), posedge D, tsetup$D$CLK, thold$D$CLK, NOTIFIER);

    $setuphold(posedge CLK &&& (flag == 1), negedge D, tsetup$D$CLK, thold$D$CLK, NOTIFIER);

    // MINIMUM WIDTH CHECKING
    $width(negedge CLK, tminpwl$CLK, 0, NOTIFIER);
    $width(posedge CLK, tminpwh$CLK, 0, NOTIFIER);

  endspecify
`endif

endmodule

`endif
dff.model.xml
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<?xml version="1.0"?>
<models>
  <model name="DFF">
    <input_ports>
      <port is_clock="1" name="CLK"/>
      <port clock="CLK" name="D"/>
    </input_ports>
    <output_ports>
      <port clock="CLK" name="Q"/>
    </output_ports>
  </model>
</models>
dff.pb_type.xml
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<?xml version="1.0"?>
<pb_type xmlns:xi="http://www.w3.org/2001/XInclude" blif_model=".subckt DFF" name="DFF" num_pb="1">
  <clock name="CLK" num_pins="1"/>
  <input name="D" num_pins="1"/>
  <output name="Q" num_pins="1"/>
  <T_setup clock="CLK" port="DFF.D" value="10e-12"/>
  <T_hold clock="CLK" port="DFF.D" value="10e-12"/>
  <T_clock_to_Q clock="CLK" max="10e-12" port="DFF.Q"/>
</pb_type>

Clock associations inference

  • Automatic inference is signal is associated with any clock and include the info in the model

  • Automatic clock detection (signals named clk are considered as clocks)

Blackbox detection

  • Model of the leaf pb_type is generated

  • Leaf pb_type XML is generated

Timings

  • All the timings defined for wires with attributes should be included in pb_type XML