Clock multiplexing primitive

This is an example of modeling a clock mux/buffer which utilizes both clock inputs and clock outputs.

By default, clocks are excluded from the combinational sink list. IE They do not have combinational_sink_ports property associated with them. However, clock multiplexers violate this rule as their input clocks do not drive any sequential logic. They are passed to output(s) instead. VPR requires Clock buffers & muxes to be defined in this way.

V2X provides the attribute (* COMB_INCLUDE_CLOCKS *) that when specified on an output port makes appear on the combinational_sink_ports list of its related input port(s) even if it is marked as a clock input.

/home/docs/checkouts/readthedocs.org/user_builds/python-symbiflow-v2x/checkouts/latest/docs/examples/clock_mux/gmux.sim.v
tests/clock_mux/gmux.sim.v
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// A model of a clock multiplexer with two clock inputs, one clock output and
// a select input.

(* whitebox *)
module GMUX (IP, IC, IS0, IZ);

    // 1st clock input
    (* CLOCK *)
    input  wire IP;

    // 2nd clock input
    (* CLOCK *)
    input  wire IC;

    // Select input
    input  wire IS0;

    // Clock output (has to be defined as a regular output port)
    (* DELAY_CONST_IP="1e-10" *)
    (* DELAY_CONST_IC="2e-10" *)
    (* DELAY_CONST_IS0="3e-10" *)
    (* COMB_INCLUDE_CLOCKS *)
    output wire IZ;

    // Behavioral model:
    assign IZ = IS0 ? IC : IP;

endmodule

In this example the (* COMB_INCLUDE_CLOCKS *) attribute is set on the IZ output making it appear in combinational sinks lists of its associated clock input ports.

gmux.model.xml
<?xml version="1.0"?>
<models>
  <model name="GMUX">
    <input_ports>
      <port combinational_sink_ports="IZ" is_clock="1" name="IC"/>
      <port combinational_sink_ports="IZ" is_clock="1" name="IP"/>
      <port combinational_sink_ports="IZ" name="IS0"/>
    </input_ports>
    <output_ports>
      <port name="IZ"/>
    </output_ports>
  </model>
</models>
gmux.pb_type.xml
<?xml version="1.0"?>
<pb_type xmlns:xi="http://www.w3.org/2001/XInclude" blif_model=".subckt GMUX" name="GMUX" num_pb="1">
  <clock name="IC" num_pins="1"/>
  <clock name="IP" num_pins="1"/>
  <input name="IS0" num_pins="1"/>
  <output name="IZ" num_pins="1"/>
  <delay_constant in_port="GMUX.IC" max="2e-10" out_port="GMUX.IZ"/>
  <delay_constant in_port="GMUX.IP" max="1e-10" out_port="GMUX.IZ"/>
  <delay_constant in_port="GMUX.IS0" max="3e-10" out_port="GMUX.IZ"/>
</pb_type>