Force input as regular input by setting the CLOCK attribute¶
input wire a
should be detected as a clock because it drives the flip flop. However, it has the attribute CLOCK set to 0 which should force it to be a regular input.
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 | /*
* `input wire a` should be detected as a clock because it drives the flip
* flop. However, it has the attribute CLOCK set to 0 which should force it
* to be a regular input.
*/
module BLOCK(a, b, c);
(* CLOCK=0 *)
input wire a;
input wire b;
output wire c;
reg r;
always @ ( posedge a ) begin
r <= b;
end
assign c = r;
endmodule
|
As such, the is_clock
attribute of the a
port is not set.
<?xml version="1.0"?>
<models>
<model name="BLOCK">
<input_ports>
<port clock="a" combinational_sink_ports="c" name="a"/>
<port clock="a" name="b"/>
</input_ports>
<output_ports>
<port clock="a" name="c"/>
</output_ports>
</model>
</models>
<?xml version="1.0"?>
<pb_type xmlns:xi="http://www.w3.org/2001/XInclude" blif_model=".subckt BLOCK" name="BLOCK" num_pb="1">
<input name="a" num_pins="1"/>
<input name="b" num_pins="1"/>
<output name="c" num_pins="1"/>
</pb_type>