Force input as regular input by setting the CLOCK attribute

input wire a should be detected as a clock because it drives the flip flop. However, it has the attribute CLOCK set to 0 which should force it to be a regular input.

/home/docs/checkouts/readthedocs.org/user_builds/python-symbiflow-v2x/checkouts/latest/docs/examples/clocks/input_attr_not_clock/block.sim.v

tests/clocks/input_attr_not_clock/block.sim.v
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/*
 * `input wire a` should be detected as a clock because it drives the flip
 * flop. However, it has the attribute CLOCK set to 0 which should force it
 * to be a regular input.
 */
module BLOCK(a, b, c);
    (* CLOCK=0 *)
    input wire a;
    input wire b;
    output wire c;
    
    reg r;
    always @ ( posedge a ) begin
      r <= b;
    end
    assign c = r;
endmodule

As such, the is_clock attribute of the a port is not set.

block.model.xml
<?xml version="1.0"?>
<models>
  <model name="BLOCK">
    <input_ports>
      <port clock="a" combinational_sink_ports="c" name="a"/>
      <port clock="a" name="b"/>
    </input_ports>
    <output_ports>
      <port clock="a" name="c"/>
    </output_ports>
  </model>
</models>
block.pb_type.xml
<?xml version="1.0"?>
<pb_type xmlns:xi="http://www.w3.org/2001/XInclude" blif_model=".subckt BLOCK" name="BLOCK" num_pb="1">
  <input name="a" num_pins="1"/>
  <input name="b" num_pins="1"/>
  <output name="c" num_pins="1"/>
</pb_type>