Set inputs as clock by name (multiple clock inputs)

input wire rdclk and input wire wrclk have clk in their names, hence are recognized as clock inputs by v2x.

tests/clocks/multiple_inputs_named_clk/multiple_inputs_named_clk.sim.v

/*
 * `input wire rdclk` and `input wire wrclk` should be detected as a clock
 * despite this being a black box module.
 */
(* whitebox *)
module BLOCK(a, rdclk, b, wrclk, c, o);
  input wire a;
  input wire rdclk;
  input wire b;
  input wire wrclk;
  input wire c;
  output wire o;
endmodule

As such, the is_clock attribute of the rdclk and wrclk ports are set to 1.

multiple_inputs_named_clk.model.xml

<?xml version="1.0"?>
<models>
  <model name="BLOCK">
    <input_ports>
      <port name="a"/>
      <port name="b"/>
      <port name="c"/>
      <port is_clock="1" name="rdclk"/>
      <port is_clock="1" name="wrclk"/>
    </input_ports>
    <output_ports>
      <port name="o"/>
    </output_ports>
  </model>
</models>