AND gate

This is an AND gate

and.sim.v

module AND (
    input  A,
    input  B,
    output Y
);

    assign Y = A & B;

endmodule

The gate model generated by V2X

and.model.xml

<?xml version="1.0"?>
<models>
  <model name="AND">
    <input_ports>
      <port combinational_sink_ports="Y" name="A"/>
      <port combinational_sink_ports="Y" name="B"/>
    </input_ports>
    <output_ports>
      <port name="Y"/>
    </output_ports>
  </model>
</models>

The gate pb_type generated by V2X

and.pb_type.xml

<?xml version="1.0"?>
<pb_type xmlns:xi="http://www.w3.org/2001/XInclude" blif_model=".subckt AND" name="AND" num_pb="1">
  <input name="A" num_pins="1"/>
  <input name="B" num_pins="1"/>
  <output name="Y" num_pins="1"/>
</pb_type>