Set input as clock by name (regex)

An input wire can be set as a clock by having clk in its name (case insensitive).

tests/clocks/input_named_regex/block.sim.v

(* whitebox *)
module BLOCK(
    input  wire clk,
    input  wire Clk,
    input  wire CLK,
    input  wire clkX,
    input  wire clkBus,
    input  wire sys_clk,
    input  wire sys_clk10,
    input  wire regular_input,
    output wire o
);

endmodule

As such, the is_clock attribute of wires with a variation of clk in their name is set to 1.

block.model.xml

<?xml version="1.0"?>
<models>
  <model name="BLOCK">
    <input_ports>
      <port is_clock="1" name="CLK"/>
      <port is_clock="1" name="Clk"/>
      <port is_clock="1" name="clk"/>
      <port is_clock="1" name="clkBus"/>
      <port is_clock="1" name="clkX"/>
      <port name="regular_input"/>
      <port is_clock="1" name="sys_clk"/>
      <port is_clock="1" name="sys_clk10"/>
    </input_ports>
    <output_ports>
      <port name="o"/>
    </output_ports>
  </model>
</models>

block.pb_type.xml

<?xml version="1.0"?>
<pb_type xmlns:xi="http://www.w3.org/2001/XInclude" blif_model=".subckt BLOCK" name="BLOCK" num_pb="1">
  <clock name="CLK" num_pins="1"/>
  <clock name="Clk" num_pins="1"/>
  <clock name="clk" num_pins="1"/>
  <clock name="clkBus" num_pins="1"/>
  <clock name="clkX" num_pins="1"/>
  <clock name="sys_clk" num_pins="1"/>
  <clock name="sys_clk10" num_pins="1"/>
  <input name="regular_input" num_pins="1"/>
  <output name="o" num_pins="1"/>
</pb_type>