Skip to content
 
F4PGA Verilog to XML (V2X) 0.0-612-gcc8bebb documentation Manually set outputs as clock
Type to start searching
    • F4PGA Verilog to XML (V2X) 0.0-612-gcc8bebb documentation
    • Examples
    • Clock
    • web SymbiFlow Website
    • library_books SymbiFlow Docs
    • chat_bubble Chat
    • campaignAnnouncements
    • mail Mailing List
    • Examples
    • Show Source

    Manually set outputs as clockΒΆ

    • Manually set output as clock by setting the CLOCK attribute
    • Set output as clock by name (clk)
    Previous Set input as clock by name (regex)
    Next Manually set output as clock by setting the CLOCK attribute
    SymbiFlow
    Mailing List
    IRC
    Slack
    © Copyright 2018-2022, F4PGA Authors.
    Created using Sphinx 3.3.0. and Material for Sphinx